The present invention relates to ways of controlling the transconductance of a differential stage with active load followed by a cascode current follower (transconductor) in discrete steps. More particularly, the present invention proposes a transconductor with a digitally programmable transconductance and substantially constant DC operating point. The present invention also proposes an accurate transconductance setting that depends on a master value and on ratios of similar components integrated on the same chip.
The basic setting of the transconductance of a differential stage is through a tail current. The DC operating point is also dependent on the value of the tail current. There are certain circuit configurations, like programmable amplifiers or filters, where changing the transconductance has to be done in discrete steps, and without affecting other parameters such as the distortion level.
FIG. 1 shows a conventional digitally-programmable transconductor circuit. The transconductor circuit presented in FIG. 1 is derived from a source degenerated differential pair. It includes a current generator 30, right and left precision transconductors 40 and 50, and a degeneration resistance 60. The current generator 30 includes a left current generator 32 and a right current generator 34. The right and left precision transconductors 40 and 50 each include a right or left operational amplifier 44, 54 and a right or left PMOS transistor 46, 56. The PMOS transistor 46, 56 passes a right or left current IL or IR, and is controlled by the output of the corresponding operational amplifier 44, 54. Each of the right or left operational amplifier 44, 54 accepts a corresponding left or right voltage VL or VR at a non-inverting input 42, 52 and a feedback loop from the degeneration resistance 60 at a negative input 43, 53. The degeneration resistance 60 includes a plurality of degeneration resistors RD1, RD2, RD3, RD4, and RD5 and a plurality of programming switches SP1, SP2, SP3, SP4, SP5, and SP6. The degeneration resistors can be classified as first and second left resistors RD1 and RD2, a center resistor RD3, and first and second right resistors RD4 and RD5.
The right and left precision transconductors 40 and 50 take their feedback from taps on the plurality of degeneration resistors RD1, RD2, RD3, RD4, and RD5 through the plurality of programming switches SP1, SP2, SP3, SP4, SP5, and SP6. These switches are controlled by a plurality of switch control signals C1 to C3.
Through the selection of a particular pair of taps the resulting degeneration resistance can be properly divided. The five degeneration resistors are divided by the switches into a central resistance RC, a right lateral resistance RRL, and a left lateral resistance RLL. The lateral resistances RRL and RLL are included in the respective feedback loops of the precision transconductors 40 and 50, and the central resistance passes a side current IS. The feedback of the precision transconductors 40 and 50 forces the input voltage across the resultant center resistance RC.
Table 1 below shows an example of how the central resistance Rc and the lateral resistances RRL and RLL are determined based on the status of the programming switches SP1, SP2, SP3, SP4, SP5, and SP6.
The central resistance Rc defines the AC current generated by the transconductor. By changing the position of the taps, the value of the resistor exposed to the input voltage changes. This yields an equivalent transconductance as follows:                               g          m                =                                                            I                R                            -                              I                L                                                                    V                R                            -                              V                L                                              =                      1                          R              C                                                          (        1        )            
Another drawback of this circuit becomes apparent at high frequency, where it is necessary to have high speed amplifiers drawing important currents for the feedback to be effective.
An implementation of a continuously adjustable transconductance circuit is presented in FIG. 2. This continuously adjustable transconductance circuit includes first and second precision transconductors 210 and 220, first through third tunable transistors TTUN1, TTUN2, and TTUN3, a plurality of resistors R connected between inputs of the transconductors 210 and 220, a capacitor C connected between outputs of the transconductors 210 and 220, and a variety of transistors T and current sources 260.
The precision transconductors 210 and 220 each include an operational amplifier 212, 222 and a transistor TT1, TT2, and the transconductors 210 and 220 are connected to have degeneration resistor.
The output currents iout1 and iout2 of the circuit are steered by the tunable transistors TTUN1, TTUN2, and TTUN3 into the inputs of a folded-cascode. Complementary weighted currents are summed on the low impedance of the folded-cascode, providing opposite AC currents to the outputs.
Each of the tunable transistors TTUN1, TTUN2, and TTUN3 provide a respective tunable resistance RTUN1, RTUN2, or RTUN3. The resistance presented by each of the tunable transistors TTUN1 (RTUN1), TTUN2 (RTUN2), and TTUN3 (RTUN3) varies with first and second control voltages V1, and V2 supplied to the inputs of the transistors TTUN1, TTUN2, and TTUN3. If, for example, the first and third tunable transistors TTUN1 and TTUN3 are identical, then the first and third tunable resistances will also be identical (RTUN1=RTUN3), since they both receive the first control voltage V1. For differential output currents from the transconductor i1=ii, i2=(xe2x88x92ii), we have:                                           i            A                    =                                    (                                                R                  TUN2                                                                      2                    ⁢                                          xe2x80x83                                        ⁢                                          R                      TUN1                                                        +                                      R                    TUN2                                                              )                        ⁢                          i              1                                      ⁢                  
                                    (        1        )                                          i          B                =                              -                          (                                                R                  TUN2                                                                      2                    ⁢                                          xe2x80x83                                        ⁢                                          R                      TUN1                                                        +                                      R                    TUN2                                                              )                                ⁢                      i            1                                              (        2        )            
The fraction       R    TUN2              2      ⁢              xe2x80x83            ⁢              R        TUN1              +          R      TUN2      
of the current generated by the input transconductor that is distributed to the output changes with RTUN1=RTUN3, RTUN2, i.e., this fraction of the current is a function of RTUN1, RTUN2, and RTUN3. The global transconductance appears as a fraction of the input stage transconductance. This ratio is voltage controlled. The dependence of the output current on the individual xe2x80x9cresistorxe2x80x9d values is not linear unless by electronic means the sum (2RTUN1+RTUN2) is kept constant.
The current sources 260 are preferably bias current sources, and the resistors R form a main transconductance setting. In this case, the transconductance of the stage is a fraction (depending upon V1, and V2) of (1/R).
Another way of steering the current of the input transconductor is shown in FIG. 3. The circuit of FIG. 3 includes an input transconductor 305, voltage control current steering circuit 310, a common mode feedback circuit 330, and a plurality of transistors T.
The input transconductor 305 includes first and second sections 350 and 360, each functioning as a differential amplifier. The first section 350 includes first through fourth transistors T1, T2, T3, and T4. The second section 360 includes fifth through seventh transistors T5, T6, and T7.
The voltage controlled current steering circuit 310 includes eighth through eleventh transistors T8, T9, T10, and T11, formed into two differential pairs. The eighth and ninth transistors T8 and T9 form one differential pair, and the tenth and eleventh transistors T10 and T11, form the other differential pair.
A fraction of the current generated by the input transconductor 305 is transmitted to the outputs iout1 and iout2 through a voltage controlled current steering circuit composed of the two differential pairs (formed from the differential transistors T8, T9, T10, and T11). The circuit has the disadvantages of requiring a high supply voltage to accommodate the various stacked stages, and experiencing difficulty with digitally controlling the current steering.
FIG. 4 shows a design for a switchable amplifier. This switchable amplifier is similar to the circuit of FIG. 1 in that a resistor string is used as a degeneration resistor for an enhanced transconductor (T1-T3; T2-T4), i.e., (T1 and T3) and (T2 and T4) each form a composite transistor. This switchable amplifier includes first through sixth transistors T1 to T6, a degeneration resistance 410, first and second resistors 422 and 424, and first through fourth current sources 432, 434, 436, and 438.
The degeneration resistance 410 includes 2n degeneration resistors RA1 to RAn and RB1 to RBn, and (2n+2) switches SA1 to SA(n+1) and SB1 to SB(n+1), where n is an integer greater than 1. As with the circuit of FIG. 1, the switches SA1 to SA(n+1) and SB1 to SB(n+1) are controlled to create a central resistance RC and left and right lateral resistances RLL and RLR.
The current of the third and fourth transistors T3, T4 is injected into symmetrically placed taps of the degeneration resistance 410. In this way, the left and right lateral resistances RLL and RLR are included in the local feedback loops, but still conduct DC currents. In this circuit, most of the differential input voltage appears across the center resistance RC, in a manner similar to the circuit of FIG. 1.
It is thus an object of the present invention to overcome or at least minimize the various drawbacks associated with conventional techniques for controlling the transconductance of a differential stage.
In an effort to meet this and other objects of the invention, and according to one aspect of the present invention, a cascode transconductor circuit is provided, i.e., a transconductor with a cascode output stage. This cascode transconductor includes a transconductor, first through fourth resistors, a cascode circuit, and a dummy folded-cascode.
The transconductor receives first and second input voltages, and outputs first and second internal currents. The first resistor is connected between first and third nodes, and the second resistor is connected between the first node and a fifth node. The first and second resistors form a first resistive divider that receives the first internal current at the first node, and generates a third internal current at the third node.
The third resistor is connected between second and fourth nodes, and the fourth resistor connected between the second node and the fifth node. The third and fourth resistors form a second resistive divider that receives the second internal current at a second node, and generates a fourth internal current at a fourth node.
The cascode circuit receives the third and fourth internal currents and supplies first and second output currents. The dummy folded-cascode connected to the fifth node. The dummy folded-cascode may be a single-ended low-impedance input folded-cascode.
According to another aspect of the invention, a cascode transconductor circuit, is provided that includes a transconductor receiving first and second input voltages, and outputting first and second internal currents, a first resistor network receiving the first internal current at a first node, and generating a third internal current at a third node, a second resistor network receiving the second internal current at a second node, and generating a fourth internal current at a fourth node, and a cascode circuit receiving the third and fourth internal currents and supplying first and second output currents.
The first resistor network may comprise p first resistors connected in series between the third node and a fifth node, and (p+1) first switches, each connected between the first node and an end of one of the p first resistors, such that each first resistor is connected to two of the (p+1) first switches. Similarly, the second resistor network may comprise p second resistors connected in series between the fourth node and the fifth node, and (p+1) second switches, each connected between the second node and an end of one of the p second resistors, such that each second resistor is connected to two of the (p+1) second switches. In this case, p is an integer greater than 1.
Preferably, the ith first resistor and the ith second resistor have the same value. In this case i is an integer between 1 and p. Preferably, during operation only one of the first switches and one of the second switches are closed at a given time.
The first and second switches may each comprise a transistor controlled by one of a plurality of control signals. The first and second resistors may each comprise a transistor controlled by a bias voltage.
According to yet another aspect, a cascode transconductor circuit is provided that comprises a transconductor receiving first and second input voltages, and outputting first and second internal currents, a first R-nR network receiving the first internal current at a first node, and generating a third internal current at a third node, a second R-nR network receiving the second internal current at a second node, and generating a fourth internal current at a fourth node, and a cascode circuit receiving the third and fourth internal currents and supplying first and second output currents.
The first R-nR network may comprise p first resistors connected in series between the third node and a fifth node, (pxe2x88x921) second resistors, each connected between the fifth node and a connection between two of the p first resistors, such that each meeting of two of the p first resistors is connected to one of the (pxe2x88x921) second resistors and (p+1) first switches, each connected between the first node and an end of one of the p first resistors, such that each first resistor is connected to two of the (p+1) first switches. Similarly, the second R-nR network may comprise p third resistors connected in series between the fourth node and the fifth node, (pxe2x88x921) fourth resistors, each connected between the fifth node and a connection between two of the p third resistors, such that each meeting of two of the p third resistors is connected to one of the (pxe2x88x921) fourth resistors, and (p+1) second switches, each connected between the third node and an end of one of the p third resistors, such that each third resistor is connected to two of the (p+1) second switches.
Preferably, during operation only one of the first switches and one of the second switches are closed at a given time.
Each of the first and second switches may comprise a transistor controlled by one of a plurality of control signals.
Preferably, the 2nd through (pxe2x88x921)th first resistors and the 2nd through (pxe2x88x921)th third resistors all have a first resistance value, and the 1st and pth first resistors, the 1st and pth third resistors, the (pxe2x88x921) second resistors, and the (pxe2x88x921) fourth resistors all have a second resistance value substantially equal to an integral multiple of the first resistance value. In the case of a R-2R network, the second resistance value should be twice the first resistance value.